The present invention relates to a logical comparison circuit for use in IC test equipment.
FIG. 1 illustrates a conventional logical comparison circuit. Reference numeral 10 indicates an IC under test, 12 is a sample-hold circuit which fetches and holds therein the output signal from the IC under test 10 every sampling clock CK.sub.S, 20 is a first interleave circuit which converts a sample data signal D.sub.S from the sample-hold circuit 12 into a plurality of expanded, low-speed parallel data signals Da, Db and Dc, 30 is a second interleave circuit which converts an expected value pattern signal E into a plurality of expanded, low-speed signals Ea, Eb and Ec, 40 is a comparator circuit which compares the sample data signal and the expected value pattern signal converted by the first and second interleave circuits 20 and 30 into signals of lower frequencies and judges their match or mismatch, and 50 is a period converter which converts the comparator output into a signal of the original period.
With such test equipment, a test pattern from a pattern generator (not shown) is applied to the IC under test 10 in synchronization with a test clock CK.sub.1, the output response signal from each pin of the IC 10 is compared by the logical comparison circuit with an expected value pattern and the result of comparison is stored in a memory and analyzed. The test clock CK.sub.1 for determining the timing for the application of the test pattern is variable within two test cycles, for example. The output response signal from each pin of the IC 10 is held in the sample-hold circuit 12 by a sampling clock CK.sub.S synchronized with the test clock CK.sub.1. In the first interleave circuit 20 gates 25, 26 and 27 are enabled one by one in a repeating cyclic order, by a counter 24 which cyclically shifts its high-level output bit position upon each application thereto of the test clock CK.sub.1. Pieces of sample data D.sub.1, D.sub.2, D.sub.3, . . . are sequentially fetched into latch circuits 21, 22 and 23 by the clock CK.sub.1 passing through the gates 25, 26 and 27 one after another. By this, a sample data signal D.sub.S shown on Row A in FIG. 2 is converted to three parallel low-speed data signals Da=D.sub.1, D.sub.4, D.sub.7, . . . , Db=D.sub.2, D.sub.5, D.sub.8, . . . and Dc=D.sub.3, D.sub.6, D.sub.9, . . . , each having a three-fold period 3T as shown on Rows C, D and E in FIG. 2. Similarly, the second interleave circuit 30 is also made up of a counter 34, gates 35, 36 and 37 and latch circuits 31, 32 and 33. The second interleave circuit converts, by a system clock CK.sub.3 shown on Row G in FIG. 2, the expected value pattern signal E synchronized with a fixed system clock, shown on Row F in FIG. 2, into three low-speed data signals Ea=E.sub.1, E.sub.4, . . . , Eb=E.sub.2, E.sub.5, . . . and Ec=E.sub.3, E.sub.6, . . . as depicted on Rows H, I and J in FIG. 2. The corresponding pieces of data of the low-speed signals Da, Db, Dc and Ea, Eb, Ec, that is, D.sub.1 and E.sub.1, D.sub.2 and E.sub.2, D.sub.3 and E.sub.3, . . . are subjected to logical comparison, in pairs, by comparators 41, 42 and 43 of the comparison circuit 40 to see if the logic of the data of the signals Da, Db and Dc matches the logic of the data of the expected value pattern signals Ea, Eb and Ec. The comparators 41, 42 and 43 may each be formed by an exclusive OR circuit. In the period converter 50 the results of comparison by these comparators 41, 42 and 43 pass through gates 51, 52 and 53 in periods specified by gate signals Ga, Gb and Gc. These signals are shown on Rows K, L and M in FIG. 2, and are generated by a counter 54 which circulates in synchronization with a system clock CK.sub.2, and the gate outputs are combined by an OR gate 55 into the signal of the initial period T, which is output as a decision signal R.sub.H (shown on Row N in FIG. 2). In any of the counters 24, 34 and 54 any one of outputs of three bits is always a high-level. Upon each application of an input clock, the high-level bit position cyclically shifts on a bitwise basis. Such a counter may be formed by a ring counter, but the three-bit output counter, for example, can easily be formed using two flip-flops, one NOR gate and three inverters.
As described above, the conventional logical comparison circuit has a construction in which the sample data signal D.sub.S and the expected value pattern signal E are converted into low-speed signals each having a three-fold period. The logical comparison is made using low-speed signals having long periods. The reason for this is that the phase of the sample data signal D.sub.S may sometimes be varied. That is to say, during a test the phase of the test pattern signal to the IC under test 10 is varied by changing the phase of the test clock CK.sub.1 to check the range of phase over which the IC 10 normally operates in response to the change in the phase of the input signal. Since the response signal from the IC under test 10 is also subjected to sampling by the sampling clock CK.sub.S synchronized with the test clock CK.sub.1, the phase of the sample data signal D.sub.S also varies. As a result of this, the sample data signal D.sub.S is displaced apart in phase from the expected value pattern signal E synchronized with a fixed system clock. In such an instance, if the two signals are compared intact, there is the possibility that the cycle of the sample data signal D.sub.S and the cycle of the expected value pattern signal E deviate from each other, making it impossible to compare their corresponding cycles.
On this account, according to the prior art, the sample data signal D.sub.S and the expected value pattern signal E are both converted to signals of longer periods to thereby provide for an extended period for comparison so that the corresponding cycles of both signals overlap for the logical comparison thereof. Moreover, both signals are made low-speed by the above-mentioned extension of their periods so that they are compared in the form of low-speed signals. This permits the use of low-cost circuit elements for the logical comparison of high-speed signals. Such a conventional circuit structure as mentioned above, however, calls for two interleave circuits, and hence inevitably becomes large-scale.